CS-281 Schedule

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Date Lecture Reading Homework
Week 0:
Fri Aug 28 Introduction Syllabus Read Chapter 1
Week 1:
Mon Aug 31 Memory Model, Binary, Hex 2.1
Tues Sept 1
Wed Sept 2 Quiz; Byte Ordering, Fixed word conventions: MSB/LSB etc.
Fri Sept 4 Booleans and Bit Operations (bool.c); Integer Representations; Conversions 2.2 Datalab Out (datalab-handout.tar)
Week 2:
Mon Sept 7 Two's Complement (hexdec.cpp) 2.2-2.3
Tues Sept 8 HWLab1: Breadboard/Arduino Intro
Wed Sept 9 Quiz; Conversions, Truncation/Sign Extension, View from C/C++ 2.3
Fri Sept 11 Integer Arithmetic Lab2 Prelab Out
Sun Sept 13 6-8 p.m.: Recitation / Datalab Strategy / Open Lab Optional Session
Week 3:
Mon Sept 14 Program Encodings, Data Formats 3.1-3.3
Tues Sept 15 HWLab2: Combinational Building Blocks IC Docs; MuxValidate.cpp Lab2 Prelab Due
Wed Sept 16 Assembly Language Intro 3.4
Fri Sept 18 Operands; Movement; classexercise1.c, GDB Datalab Due by classtime; Lab3 Prelab Out
Week 4:
Mon Sept 21 Operands and movl; Stack Use Intro 3.5
Tues Sept 22 HWLab3: Combinational Logic Simplification; pot2binary.cpp
Wed Sept 23 Continue Stack Use; Arithmetic and Logic instructions 3.5
Fri Sept 25 Introduction to Control; Condition Codes; Start Basic Branching (class4.c) 3.6 thru 3.6.4 NC1: Demo of Arith/Logic Instructions through class2.c, class3.s
Week 5:
Mon Sept 28 Control: Loops 3.6.5 - 3.6.6
Tues Sept 29 HWLab4: Sensors and Actuators
Wed Sept 30 while loop translation cont'd; review ALUlibrary Project and ALUlibrary.circ template; bomblab Out
Fri Oct 2 Midterm 1 (Thursday eve)
Week 6:
Mon Oct 5 Switch statements; other loops 3.6.7, 3.8
Tues Oct 6 HWLab5: More Sensors and Servo Motor Actuator
Wed Oct 7 Data structures; Stack Discipline 3.7, 3.9 IA32-V1, IA32-V2a (A-M), IA32-V2b (N-Z)
Fri Oct 9 Finish stack convention; forloop.c, forloop.dis 3.7, 3.9 Lab6 Prelab Out
Week 7:
Mon Oct 12 Buffer Overflow 3.12
Tues Oct 13 Lab6: Sequential Circuit and FSM
Wed Oct 14 Y86 Instruction Set bomblab Due; buflab Out
Fri Oct 16 No class: Fall Study Break
Week 8:
Mon Oct 19 Class Cancelled
Tues Oct 20 HWLab7: Ant Brain - ant.tar
Wed Oct 21 Y86 Instruction Set Architecture and Encoding 4.1
Fri Oct 23 Y86 CPU Implementation I 4.3
Week 9:
Mon Oct 26 Y86 CPU Implementation II - Stage definitions and Instruction RTL buflab Due
Tues Oct 27 HWLab7 Part II: Ant Brain Continued
Wed Oct 28 Y86 SEQ Datapath in Logisim Antbrain Due (Hand in Lab Report in class and email ant.circ); Y86 ALU/Datapath Out
Fri Oct 30 Y86 SEQ Wrapup and Review for Midterm SEQ Instruction Flow for call and pop; Y86 ALU Datapath Out (cpulab-f15.tar)
Week 10:
Mon Nov 2 Midterm 2 (really Sunday at 7pm, and no class on Monday)
Tues Nov 3 Interrupts and Stepper Motor Controller: StepperMotor.zip
Wed Nov 4 Exceptional Control Flow I: Concepts to Processes 8.1, 8.2
Fri Nov 6 Exceptional Control Flow II: Fork, Exec, Process Control (slides) 8.3, 8.4 Shell Lab Out, shlab-handout.tar; Y86 ALU/Datapath Due at midnight on Sunday
Week 11:
Mon Nov 9 8.5
Tues Nov 10 Y86 Control - cpulab-f15.tar
Wed Nov 11 Exceptional Control Flow III: Signals (slides) 8.5
Fri Nov 13 6.4
Week 12:
Mon Nov 16 Memory Hierarchy I: Concepts to Caches Light Read 6.1; 6.2 and 6.3 in detail
Tues Nov 17 Final Project: Exploration CPU Hardware Lab Report due by classtime
Wed Nov 18 Memory Hierarchy II: Caches (slides) 6.4
Fri Nov 20 Memory Hierarchy II: Caches 6.5 Shell Lab Due
Thanksgiving Break: Nov 21-29
Week 13:
Mon Nov 30 Floating Point Representation 2.4 Cachelab Out (cachelab-handout.tar)
Tues Dec 1 Final Project Work
Wed Dec 2 Floating Point Conclusion (slides) 4.4
Fri Dec 4 Pipelining Detail I 4.5
Week 14:
Mon Dec 7 Pipelining Detail II (slides) Cache Lab Due
Tues Dec 8 HW Lab Final Project Completion (Demo by 5pm Wednesday)
Wed Dec 9 Midterm 3
Fri Dec 11 No class rsum Take Home Final Distributed
Takehome Final Exam - Due by normal exam time by email


© Thomas Bressoud 2015