| Week |
Day |
Topics |
Reading
Due |
Exercises
HW Due
|
1
1/15
to
1/19
|
M
|
Introduction
|
Syllabus
|
|
|
T
|
Structure and Function, Evolution
|
Ch. 1 & 2
|
|
|
W
|
Number Systems
|
Appendix A |
|
|
F
|
Computer Function, Instruction Sets
|
3.1,3.2,10.1 - 10.3 |
HW1--A.1 - A.10, all parts
|
2
1/22
to
1/26
|
M
|
No class -- MLK Observance |
|
|
|
T
|
Addressing Modes and Formats
|
Ch. 10, cont.
|
|
|
W
|
Instruction sets; 0-3 Address Machines; PowerPC ISA Register Set
|
Ch. 10.1-10.2
|
|
|
F
|
PowerPC ISA Arithmetic, Load/Store |
Ch. 10.4 |
HW2-- 10.1, 10.2, 10.6, 10.18, 10.19
|
3
1/29
to
2/2
|
M
|
Arithmetic Instructions and their Machine Code, Effective Address Calculation |
Ch. 10.4, Ch. 9.1-9.2 |
|
|
T
|
Constructing addresses; EA calculation redux; asciz v. long storage, integer representation |
9.1-9.2 |
|
|
W
|
Sign Extension; PPC ISA Branches, Compare, translating if-then, if-then-else, and while HLL constructs |
9.2, 10.4 |
|
|
F
|
Integer overflow and carry; Addressing Modes; Logical Operations
|
9.3, 10.4, 11.1, 11.2, 11.3, 11.4
|
Homework 3: Assembly Programs I
|
4
2/5
to
2/9
|
M
|
Function calls/Calling conventions
|
10.4 redux, 10A
|
|
|
T
|
Review
|
Apndx 10B
|
|
|
W
|
Midterm 1
|
|
|
|
F
|
Unsigned Integer Multiplication |
|
Homework 4: Assembly Progs 2 & 3
|
5
2/12
to
2/16
|
M
|
Midterm Redux |
9.3
|
|
|
T
|
Finish midterm redux
|
|
|
|
W
|
No Class (Snow Day!) |
|
|
|
F
|
Booth Algorithm |
|
9.2,9.5,9.6a,9.7,9.8,
9.9,9.10,9.11, and repeat 9.10 with multiplication and Booth's algorithm. |
6
2/19
to
2/23
|
M
|
Unsigned Integer Division
|
|
|
|
T
|
Floating Point Representation and Arithmetic
|
9.4
|
|
|
W
|
Floating Point, cont. Addition/Substraction/Mult/Div
|
9.5
|
|
|
F
|
Function Calling in Assembly Language |
Handout |
|
7
2/26
to
3/2
|
M
|
Digital Logic Intro; Physics |
B.1, B.2 |
|
|
T
|
Combinational circuits I |
B.3 |
DSCPU Simulator
|
|
W
|
Combinational circuits II |
B.3 |
|
|
F
|
|
|
|
8
3/5
to
3/9
|
M
|
|
|
|
|
T
|
|
|
|
|
W
|
|
|
9.23, 9.24, 9.38, 9.40, B.1 thru B.4, B.8
|
|
F
|
Midterm 2 |
|
|
9
3/19
to
3/23
|
M
|
Midterm review |
|
|
|
T
|
From primitive logic design to building blocks |
|
|
|
W
|
Multiplexers and Decoders |
|
|
|
F
|
DSCPU ALU
|
|
|
10
3/26
to
3/30
|
M
|
Sequential circuits; Clocked D master-slave flip-flop
|
B.4
|
|
|
T
|
Sequential circuits
|
|
|
|
W
|
Lab 1 |
|
|
|
F
|
Finite State Machines and designing sequential circuits |
|
ALU Logisim Circuit
|
11
4/2
to
4/6
|
M
|
Lab 2
|
|
|
|
T
|
DSCPU Datapath |
12.1,12.2
|
|
|
W
|
Hardwired control I |
12.3, Ch. 16
|
|
|
F
|
Hardwired control II |
Ch. 17
|
|
12
4/9
to
4/13
|
M
|
Microprogrammed control I
|
|
|
|
T
|
Microprogrammed control II
|
|
|
|
W
|
Lab 3
|
|
|
|
F
|
Midterm 3
|
|
|
13
4/16
to
4/20
|
M
|
Single Cycle PowerPC Datapath
|
|
DSCPU Logic Simulator
|
|
T
|
Multicycle Datapath
|
12.5,12.6
|
|
|
W
|
Pipelining
|
12.4
|
|
|
F
|
Pipelining
|
|
|
14
4/23
to
4/27
|
M
|
Memory Hierarchy
|
|
|
|
T
|
Cache Memory I
|
|
|
|
W
|
Cache Memory II
|
Ch. 4
|
|
|
F
|
Fully Associative and Set Associative Cache
|
Ch. 4
|
|
| 4/30 |
M |
RISC and CISC |
|
Cache simulator project |
