Computer Science 281 Computer Organization

Project 3

DSCPU
The Denison Simple CPU Circuit Design

Project Description

The end-result of this project is to create a circuit design realization of the DSCPU. It builds on the following course elements:

1. The instruction-execution knowledge gained in Project 1, wherein the DSCPU simulator explored the fetch/decode/execute cycle of instruction execution and divided the work into execution subphases.
2. The ALU circuit design of Project 2, wherein combinational logic was used to create the organization for an ALU appropriate for the arithmetic operations of the DSCPU.
3. The knowledge from class in designing combinational and sequential circuits, such that the finite state machine that realizes the instruction execution of the DSCPU can be implemented through control logic, combined with a given datapath.

An initial version of the datapath has been implemented for you, and may be found in the following linked Logisim circuit. You are welcome and encouraged to modify this circuit as needed to implement your CPU.

The CPU is basically the same as that defined for Project 1, with a few simplifications. First, we will only use a single Flag register, the Z flag. Second, we will limit ourselves to 16 instructions plus the HALT instruction. Third, we will replace the CLAC instruction with the MVI instruction. The resultant definition of the DSCPU follows:

Registers

There are 3 registers directly controlled by the programmer:

The DSCPU also contains several registers in addition to those specified in the instruction set:

Memory

The DSCPU can address up to 65536 bytes of physical memory, mem. Addresses are 16 bits in length, and every memory byte is accessible by an address in the range 0 to 65535. Due to the limit of addresses for memory devices in Logisim, the maximum memory address for the DSCPU circuit is 4095.

Reads and writes from/to memory and achieved through the use of AR and DR. To perform a read, AR is loaded with the desired address, a, and then a memory read is requested. The completion of the read results in the contents, mem[a], in DR. To perform a write, AR is loaded with the desired address, a, and the data value to be written, d, is loaded into DR. The memory write is then requested.

Instruction Set

In the following table, an A operand refers to a 16-bit memory address and is composed of the two bytes (MSB followed by LSB) following the opcode in memory. An I operand refers to an 8-bit immediate value and is found in the byte immediately following the opcode in memory.

Assignment

Use Logisim and the provided DSCPU datapath to combine with your ALU from Project 2 and create the control logic to implement the DSCPU CPU. You may implement the control function either through hardwired or through microprogrammed control.

Program Execution

1. Your DSCPU realization must allow a load of Logisim memory from a text file, where the file contains the program to be executed.
2. Once loaded, your program should support the execution of the program by use of a Logisim "Ticks Enabled" command. You should also allow single-stepping of the execution by making a single clock device available at the top level circuit submitted, so that testing can occur by using the probe tool to manually advance the clock.
3. Begin executing the program, using your designed control circuit. Datapath register values of, at a minimum, AC, R, PC, and Z must be visible at the top level circuit.
4. Execution of a HALT instruction terminates the simulation. Subsequent clock ticks (manual or automatic) should not change the state of any register further.

Deliverables

Documentation

Good documentation is an important deliverable for this project. It will involve at least the following elements:

1. Datapath and control signal documentation. Part of the project is to complete the datapath by adding the ALU from Project 2 and by adding Muxes and other elements so that every instruction has a realization in the datapath. Your finished datapath should be documented, with a complete datapath picture and sufficient prose so that I can understand your datapath based solely on knowing what your starting point (dscpu2.circ) was. ... this means that I should not have to trace control lines and interpret control values to muxes in order to understand how your datapath operates.
2. Control Circuit Design documentation. The substance of this documentation depends on whether you choose a hardwired design or a microprogrammed design. In either case, it should lead me through the design process:
   1. For hardwired control, the control circuit design documentation should (i) include the finite state machine for execution of the entire instruction set, and clearly indicate every state transition with the input state that causes the transition and the output control signals, (ii) present a truth table that realizes the finite state machine, (iii) documents any auxiliary combinational logic used to simplify the hardwired control implementation.
   2. For microprogram control, the control circuit design documentation should include (i) the definition of the microinstruction format, (ii) the design of the microsequencer, (iii) a well documented microprogram for the instruction set, (iv) any sequence dispatch or other auxiliary logic to simplify the microprogram control.
3. Any other documentation that will help me to understand what you have done and what particulaly important design features your realization may possess.

Logisim Circuit

You obviously need to also submit your actual circuit(s). Make sure you include all circuits required for me to execute your CPU.

Your finished project must be submitted via email.

 

Best of luck, oh hardware designers of the future!