Computer Science 281
Computer Organization

Denison

Week Day Topics Reading
Due
HW / Project
Due
1 Computer Systems Overview
1/14
to
1/18
M Course Admin; Computer Systems Architecture Syllabus
T Lab: Learning the tools PH B.1-B.2
W Hello World life cycle; Assembly Language Intro PH A.1-A.4
F SPIM. Operations and operands. Instruction formats. PH A.9-A.10  
2 Assembly Language Basics
1/21
to
1/25
M No class -- MLK Observance    
T Lab: Logisim and Breadboard -- Design Process    
W Assembly Language -- Process Memory and TopLevel Structure PH Ch.1, 2.1-2.3  
F First instructions: li, la (pseudo), add, lw PH 2.1-2.3 Homework 1
3 Assembly Language
1/28
to
2/1
M More on load/store; instruction encoding; br/j PH 2.4  
T Lab: Truth table simplification -- K-map    
W Floating point useful instructions; Load/store review; Instruction encoding    
F Conditionals and Loops in Assembly; Logicals PH 2.5-2.6 Homework 2
4 Integer Representation
2/4
to
2/8
M Loops cont., Number systems Intro PH 3.1-3.2  
T Lab: 3-bit adder    
W Two's complement and Integer addition/subtraction; branch offset and encoding PH 3.3, 2.9  
F Functions in assembly language; homework help PH 2.7 Homework 3
5 Assembly Functions
2/11
to
2/15
M More on Functions in assembly language    
T Lab: 3-bit two input multiplexor  
W Midterm1  
F No class    
6  
2/18
to
2/22
M Building a simulator for the MIPS ISA -- infrastructure  
T Lab: Midterm redux  
W Function calling conventions; Addressing modes PH 2.7, 2.9
F Integer Multiplication PH 3.4
7  
2/25
to
2/29
M     Project 1 Phase 1
T Lab: Introduction to Digital Memory    
W      
F     Mult/Div Practice
8  
3/3
to
3/7
M Floating Point Format; Jump Tables   Project 1 Phase 2
T Lab: Finite State Machines  
W Floating Point Format    
F Floating Point Operations -- Addition and Multiplication   Project 1 Phase 3
9  
3/17
to
3/21
M Performance -- CPI and CPU time PH 4
T Lab: FSM and Garage Door Opener  
W MIPS Single Cycle Datapath Intro   Final MIPS Simulator
F MIPS Single Cycle Datapath -- add, sub, slt, and, or PH 5.1-5.3
10  
3/24
to
3/28
M MIPS Single Cycle Datapath -- addi, lw, sw    
T Lab: MIPS ALU    
W Conclude single cycle datapath, start control    
F MIPS single cycle control   ALU Project
11  
3/31
to
4/4
M Midterm2    
T Lab: MIPS Single Cycle Datapath and Control    
W Multicycle Motivation / Performance Improvements    
F Multicycle Datapath    
12  
4/7
to
4/11
M Muticycle Control    
T Lab: MIPS Multicycle Datapath and Control   Single Cycle Datapath/Control Due
W CPU Pipelining Introduction    
F Midterm 2 Review    
13  
4/14
to
4/18
M Huttenlocher talk and lunch    
T Lab: Huttenlocher talk    
W MIPS Pipelined Datapath   Multicycle Datapath/Control Due
F Academic Awards Convocation    
14  
4/21
to
4/25
M Memory Hierarchy and Cache Memory    
T Lab/Final Homework: MIPS Caches    
W      
F     Cache Homework turnin
4/28 M Midterm 3    



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Last updated: 08/20/04.