MIPS Arithmetic and Logic Unit (ALU)
ALU Description
The
following ALU description specifies an Arithmetic and Logic Unit that
can serve the needs of our hardware realization of the MIPS CPU
datapath. It supports 6 operations (AND, OR, add, sub, slt, and
NOR) in a combinational circuit that calculates a 32-bit output based
on two 32-bit inputs and a 4-bit input specifying the ALU operation to
perform. The ALU also computes three flag bits, C, V, and Z.
Your ALU should be self contained in a single circuit, and the package should conform to the top-level example below
Submission will be a file named ALU.circ, containing (at least) an ALU subcircuit and a main circuit that looks like the above. You should include a one-page description of your design. This description should allow me to navigate the circuits making up your ALU with their purpose, control, and interconnection.
The major component in grading the ALU will occur in a live demonstration, showing the operation of your ALU for a set of test cases of my own devising.
Flag Bits
| Flag | Width | Description |
| Z | 1 | Zero Flag: This bit is updated as a result of all operations. If the result of an operation is zero, then Z is asserted. If the result of an operation is not zero, then Z is 0. |
| V | 1 | Overflow Flag: For arithmetic operations, this bit is asserted if the carry into the most significant bit of the result does not equal the carry out of the most significant bit of the result of the last arithmetic operation, and is deasserted otherwise. For logical operations (AND, OR, and NOR), this bit is always deasserted. |
| C | 1 | Carry Flag: This bit reflects the result of the carry out of the last operation. If data is treated as unsigned and the operation is arithmetic, this bit indicates the carry out (or borrow for subtract) of the last operation. For logic operations, this bit is always 0. |
ALU Operations
In the following table, A and B refer to the two 32-bit inputs to the ALU, and F refers to the 32-bit result.| Function | ALU control | Semantics |
| AND | 0000 | F = A & B (bitwise AND); Z update, V,C=0 |
| OR | 0001 | F = A | B (bitwise OR); Z update, V,C=0 |
| add | 0010 | F = A + B; Z,V,C update |
| sub | 0110 | F = A - B; Z,V,C update |
| slt | 0111 | F = (A < B) ? 1 : 0 |
| NOR | 1100 | F = ~ ( A | B ) (bitwise NOR); Z update, V,C=0 |
Assignment
Using the Logisim (2.1.6) digital logic design and simulator package, design and implement the above-described MIPS ALU. You must only use component elements from the "Base" and "Gates" categories, and you should exhibit clean hierarchical design. Appendix B from your book develops a design for this ALU and you are welcome to follow this development. Maximum credit will be given for implementing Carry-Lookahead addition instead of Ripple-Carry addition.Your ALU should be self contained in a single circuit, and the package should conform to the top-level example below
Submission will be a file named ALU.circ, containing (at least) an ALU subcircuit and a main circuit that looks like the above. You should include a one-page description of your design. This description should allow me to navigate the circuits making up your ALU with their purpose, control, and interconnection.
The major component in grading the ALU will occur in a live demonstration, showing the operation of your ALU for a set of test cases of my own devising.