| Week |
Day |
Topics |
Reading
Due |
Exercises
HW Due
|
1
1/16
to
1/20
|
M
|
Introduction
|
Syllabus
|
|
|
W
|
Structure and Function, Evolution
|
Ch. 1 & 2
|
|
|
R
|
Number Systems
|
Appendix A |
|
|
F
|
Computer Function, Instruction Sets
|
3.1,3.2,10.1 - 10.3 |
|
2
1/23
to
1/27
|
M |
No class -- MLK Observance |
|
HW1--A.1 - A.10, all parts |
|
W
|
Addressing Modes and Formats
|
Ch. 10, cont.
|
|
|
R
|
Instruction sets; 0-3 Address Machines; PowerPC ISA Register Set
|
Ch. 10.1-10.2
|
|
|
F
|
PowerPC ISA Arithmetic, Load/Store |
Ch. 10.4 |
|
3
1/30
to
2/3
|
M
|
Arithmetic Instructions and their Machine Code, Effective Address Calculation |
Ch. 10.4, Ch. 9.1-9.2 |
|
|
W
|
Constructing addresses; EA calculation redux; asciz v. long storage, integer representation |
9.1-9.2 |
HW2 10.1, 10.2, 10.6, 10.18, 10.19
Assembly1
|
|
R
|
Sign Extension; PPC ISA Branches, Compare, translating if-then, if-then-else, and while HLL constructs |
9.2, 10.4 |
|
|
F
|
Integer overflow and carry; Addressing Modes; Logical Operations
|
9.3, 10.4, 11.1, 11.2, 11.3, 11.4
|
|
4
2/6
to
2/10
|
M
|
Function calls/Calling conventions
|
10.4 redux, 10A
|
|
|
W
|
Review
|
Apndx 10B
|
HW3: 9.5, 9.7, 9.11; 10.3; 11.1, 11.3, 11.17, 11.18
Assemby for binary GCD
|
|
R
|
Midterm 1
|
|
|
|
F
|
Parameter passing; Endian-ness |
|
|
5
2/13
to
2/17
|
M
|
Project discussion; Parameter block; begin Integer Multiplication |
9.3
|
|
|
W
|
Integer multiplication cont.
|
|
|
|
R
|
Booth's algorithm
|
|
|
|
F
|
Unsigned Integer Division; Floating Point Intro
|
9.4
|
Project1
|
6
2/20
to
2/24
|
M
|
Floating Point, cont. Addition/Substraction/Mult/Div
|
9.5
|
|
|
W
|
Digital Logic Intro; Physics |
B.1, B.2 |
HW4 Due
|
|
R
|
Combinational circuits I |
B.3 |
|
|
F
|
Combinational circuits II |
B.3 |
|
7
2/27
to
3/3
|
M
|
Sequential circuit intro
|
B.4
|
|
|
W
|
Sequential circuits; Clocked D master-slave flip-flop
|
|
|
|
R
|
Finite State Machines and designing sequential circuits
|
|
|
|
F
|
No class
|
|
|
8
3/6
to
3/10
|
M
|
DSCPU Datapath |
|
|
|
W
|
|
|
|
|
R
|
|
|
HW 5: 9.20 (as positive and use unsigned alg.), 9.23, 9.24, 9.38, 9.40, B.1, B.8 (a,b) B.11
|
|
F
|
Midterm 2
|
|
|
9
3/20
to
3/24
|
M
|
DSCPU Datapath redux; Hardwired control intro |
|
|
|
W
|
Hardwired control continued
|
|
|
|
R
|
Microprogrammed control I
|
|
|
|
F
|
Microprogrammed control II
|
|
|
10
3/27
to
3/31
|
M
|
Processor/Register Organization
|
12.1,12.2
|
HW6, Booth and unsigned div. in asmbly for DSCPU sim.
|
|
W
|
Instruction Cycle
|
12.3,12.4
|
|
|
R
|
Single Cycle PowerPC Datapath
|
Ch. 16 |
|
|
F
|
Single Cycle PowerPC Datapath
|
|
|
11
4/3
to
4/7
|
M
|
Multicycle Datapath
|
Ch. 17
|
Extra Credit Post
|
|
W
|
Multicycle Datapath
|
|
|
|
R
|
Pipelining
|
12.5,12.6
|
|
|
F
|
Pipelining
|
|
|
12
4/10
to
4/14
|
M
|
Review
|
|
|
|
W
|
Midterm 3
|
|
|
|
R
|
Memory Hierarchy
|
|
|
|
F
|
Cache Memory I
|
Ch. 4
|
Project 3
|
13
4/17
to
4/21
|
M
|
Cache Memory II
|
Ch. 4
|
|
|
W
|
Fully Associative and Set Associative Cache
|
|
|
|
R
|
|
|
|
|
F
|
|
|
|
14
4/24
to
4/28
|
M
|
|
|
|
|
W
|
|
|
|
|
R
|
|
|
|
|
F
|
|
|
|
| 5/1 |
M |
|
|
Project 4 |
